1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, and in particular, to a method for forming a flash memory.
2. Description of the Prior Art
Flash memory is a common type of non-volatile memory. Flash memory cells may include a source region and a drain region that is spaced apart from the source region by an intermediate channel region. A memory cell, including a charge structure (e.g., a floating gate, a charge trap, or other similar structure), is disposed over the channel region and is electrically isolated from the other elements by a dielectric material, such as an oxide. For example, a tunnel dielectric material (which may also be referred to in the art as a “gate dielectric” material) may be disposed between the charge structure and the channel region. A control gate, of the memory cell, is located over the charge structure. The control gate may be electrically separated from the charge structure by a charge block region, such as another dielectric layer that may be referred to in the art as an “inter-poly dielectric” (IPD), an “intergate insulator,” or an “intergate dielectric.” Thus, the charge structure may be configured as a floating gate that is electrically “floating” so that it is insulated from both the channel and the control gate.
To improve the properties of gates and gate interconnects even further, integrated circuit manufacturers are investigating the use of pure metal layers. Tungsten, for example, is of particular interest because it is relatively inexpensive, has a high melting point (approximately 3,410 degrees C.), and is known to be compatible with current manufacturing techniques.
The use of unreacted tungsten metal as a conductive word line layer can create certain problems during the fabrication process of the integrated circuit. The word line materials often must be capable of withstanding high temperature processing in an oxidizing environment. For example, shortly after the word line stack is patterned, a source/drain reoxidation is performed to repair damage that occurs to the gate oxide near the corners of source and drain regions as a result of etching the word line. The source/drain reoxidation reduces the electric field strength at the gate edge by upwardly chamfering the edge, thereby reducing the “hot electron” effect that can cause threshold voltage shifts.
However, during such a reoxidation process, exposed tungsten along the edges or sidewalls of the stack is converted quickly to tungsten trioxide gas at high temperatures in the presence of oxygen. Moreover, sublimation of the tungsten oxide is not self-limiting. The oxidation of the tungsten layer as well as oxidation of the barrier layer degrades the electrical properties of the word line.
In order to resolve the issues mentioned above, one method is forming a liner (such as a silicon nitride layer) on the word line stack before the reoxidation process is performed, so as to protect the tungsten from oxygen outside. However, other issues will still occur. For example, the thickness of the SiN liner should large enough (such as larger than 3 nm) to prevent the tungsten from oxidation, but if the thickness of the SiN liner is too big (such as larger than 2 nm), the SiN liner will easily remain on the corner of the word line stack and contact the exposed gate dielectric. In this way, during the ashing process for forming the lightly-doped drain (LDD), the nitrogen impurities in the SiN layer will penetrate and contaminate the gate dielectric, and this damage may result in degraded performance (e.g., increased resistance and capacitance) of the resulting memory cell. Furthermore, some conventional methods for forming a liner cannot be harmoniously integrated into the standard processes. For example, the liner may cause the reoxidation process to be insufficient or deteriorated. Thus, fabricating memory devices, including flash memory devices, without degradation to performance is often a challenge.
Fabricating memory cells often involves patterning a conductive material of the control gate region before patterning a conductive material of the charge structure region. After patterning the control gate region, but before patterning the charge structure region, a liner may be formed on the conductive material of the control gate region to provide protection to the conductive material during the latter (i.e., “subsequent”) patterning process in which the conductive material of the charge structure region is patterned. Nonetheless, conventional liners may not survive the subsequent patterning process and, as such, may leave at least partially exposed the conductive material of the control gate region. The exposure may result in damage to the conductive material of the control region. The damage may be in the form of any one of roughened sidewalls, undercuts at interfaces with neighboring regions, and decreased widths relative to the initially-patterned control gate region. This damage may result in degraded performance (e.g., increased resistance and capacitance) of the resulting memory cell.
Thus, fabricating memory devices, including flash memory devices, without degradation to performance is often a challenge.